1. Field of the Invention
The present invention relates to modeling of a semiconductor integrated circuit, and more particularly to a modeling circuit of a field-effect transistor (FET) reflecting electrostatic-discharge characteristics.
2. Description of the Related Art
In the fabrication of semiconductor memory devices, designing an integrated circuit including function blocks is essential. In the process of designing an integrated circuit, advance verification of whether the integrated circuit is operating properly is needed. The Software Process Improvement and Capability dEtermination (SPICE) is widely used as a simulator that verifies an operation of an integrated circuit. The SPICE can perform modeling of various devices that are included in the integrated circuit using resistors, capacitors, and current sources reflecting electrical characteristic of the devices. In particular, a study on modeling of a Metal Oxide Semiconductor (MOS) transistor is continuously progressed because the MOS transistor is the most widely used device in integrated circuits.
As a design rule of a semiconductor device is ever-decreasing and, thus, a degree of integration of the semiconductor device is ever-increasing, a concern on electrostatic discharge (ESD) increases. The semiconductor device includes an ESD protection circuit used to prevent electric charge abnormally incoming from pads of the semiconductor device.
FIG. 1 is a circuit diagram illustrating an example of a semiconductor integrated circuit that includes an ESD protection circuit.
Referring to FIG. 1, the semiconductor integrated circuit includes an input pad 10, an ESD protection circuit 20, and an internal circuit 30. The ESD protection circuit 20 includes a first diode D1 and a second diode D2. The internal circuit 30 includes, for example, a buffer comprised of a PMOS transistor MP1 and an NMOS transistor MN1. The ESD protection circuit 20 limits a magnitude of a voltage of a node N1, to which the input pad 10 and the internal circuit 30 are coupled, within a predetermined range by providing a current path when an over-voltage due to an ESD event is applied to the input pad 10. Therefore, the internal circuit 30 is protected.
FIG. 2 is a circuit diagram illustrating another example of a semiconductor integrated circuit that includes an ESD protection circuit.
Referring to FIG. 2, the semiconductor integrated circuit includes an input pad 10, an ESD protection circuit 20a, and an internal circuit 30. The ESD protection circuit 20a includes a gate-coupled NMOS transistor (GCNMOS) MN2, of which a gate is coupled to the ground GND. The internal circuit 30 includes, for example, a buffer comprised of a PMOS transistor MP1 and an NMOS transistor MN1. The ESD protection circuit 20a limits a magnitude of a voltage of a node N1, to which the input pad 10 and the internal circuit 30 are coupled, within a predetermined range by providing a current path when an over-voltage due to an ESD event is applied to the input pad 10. Therefore, the internal circuit 30 is protected.
The gate-coupled NMOS transistor MN2 shown in FIG. 2 is also called a gate-grounded NMOS transistor (GGNMOS) because its gate is coupled to the ground GND.
FIG. 3 is a circuit diagram illustrating still another example of a semiconductor integrated circuit that includes an ESD protection circuit.
Referring to FIG. 3, the semiconductor integrated circuit includes an input pad 10, an ESD protection circuit 20b, and an internal circuit 30. The ESD protection circuit 20b includes a gate-coupled NMOS transistor MN3, which is coupled between a node N1 and the ground GND, a capacitor C1, and a resistor R1. The capacitor C1 is coupled between a gate and a drain of the gate-coupled NMOS transistor MN3, and the resistor R1 is coupled between the gate and a source of the gate-coupled NMOS transistor MN3. The internal circuit 30 includes, for example, a buffer comprised of a PMOS transistor MP1 and an NMOS transistor MN1. The ESD protection circuit 20b limits magnitude of a voltage of a node N1, to which the input pad 10 and the internal circuit 30 are coupled, within a predetermined range by providing a current path when a positive over-voltage due to an ESD event is applied to the input pad 10. Therefore, the internal circuit 30 is protected.
The gate-coupled NMOS transistor MN3 has the gate receiving a voltage higher than a voltage of the ground GND, unlike the gate-coupled NMOS transistor MN2 shown in FIG. 2. The node N2, i.e. the gate of the gate-coupled NMOS transistor MN3, receives the voltage that is determined by a resistor R1 and a capacitor C1.
FIG. 4 is a circuit diagram illustrating still another example of a semiconductor integrated circuit that includes an ESD protection circuit.
Referring to FIG. 4, the semiconductor integrated circuit includes an input pad 10, an ESD protection circuit 20c, and an internal circuit 30. The ESD protection circuit 20c includes a gate-coupled PMOS transistor (GCPMOS) MP2 of which a gate is coupled to a power supply voltage VDD. The internal circuit 30 includes a buffer comprised of a PMOS transistor MP1 and an NMOS transistor MN1. The ESD protection circuit 20c limits magnitude of a voltage of a node N1, to which the input pad and the internal circuit 30 are coupled, within a predetermined range by providing a current path when a negative over-voltage due to an ESD event is applied to the input pad 10. Therefore, the internal circuit 30 is protected.
FIG. 5 is a circuit diagram illustrating still another example of a semiconductor integrated circuit that includes an ESD protection circuit.
Referring to FIG. 5, the semiconductor integrated circuit includes an input pad 10, an ESD protection circuit 20d, and an internal circuit 30. The ESD protection circuit 20d includes a gate-coupled PMOS transistor MP3 that is coupled between a node N1 and a power supply voltage VDD, a capacitor C2, and a resistor R2. The capacitor C2 is coupled between a gate and a drain of the gate-coupled PMOS transistor MP3, and the resistor R2 is coupled between the gate and a source of the gate-coupled PMOS transistor MP3. The internal circuit 30 includes, for example, a buffer comprised of a PMOS transistor MP1 and an NMOS transistor MN1. The ESD protection circuit 20d limits magnitude of a voltage of a node N1, to which the input pad 10 and the internal circuit 30 are coupled, within a predetermined range by providing a current path when a negative over-voltage due to an ESD event is applied to the input pad 10. Therefore, the internal circuit 30 is protected.
The gate-coupled PMOS transistor MP3 has its gate receiving a voltage lower than the power supply voltage VDD, unlike the gate-coupled PMOS transistor MP2 shown in FIG. 4. The gate of the gate-coupled PMOS transistor MP3 receives the voltage that is determined by a resistor R2 and a capacitor C2.
FIG. 6 is a graph illustrating electrical properties of a gate-coupled NMOS transistor. In FIG. 6, the horizontal axis denotes a drain voltage V of the gate-coupled NMOS transistor MN3 shown in FIG. 2, and the vertical axis denotes a drain current I. VSB denotes a snap-back voltage and VH denotes a holding voltage. A1 is a range in which the drain voltage decreases and the drain current increases slowly, and called a snap-back area. A2 is a range in which the drain voltage hardly changes and the drain current increases sharply.
Accordingly, as a semiconductor integrated circuit includes an ESD protection circuit, there is a need to consider ESD characteristic when modeling the MOS transistor included in the semiconductor integrated circuit.
FIG. 7 is a circuit diagram illustrating a conventional modeling circuit of a gate-coupled NMOS transistor. The circuit of FIG. 7 is disclosed in PROC. 24th international conference on microelectronics, VOL. 2, pp. 619-624 in the title of ‘Design and Modeling of On-Chip Electrostatic Discharge (ESD) Protection Structures’.
Referring to FIG. 7, the modeling circuit of a gate-coupled NMOS transistor 20 includes an NMOS transistor MN4, a substrate resistor Rsub1, a bipolar transistor Q4, and a current source Igen. The NMOS transistor MN4 has a drain D, a gate G, and a source S coupled to the ground GND. One end of the substrate resistor Rsub1 is coupled to a backside SUB of a semiconductor substrate. The backside SUB of the semiconductor substrate is coupled to the ground GND. The bipolar transistor Q4 has a collector C coupled to the drain D of the NMOS transistor MN4, an emitter E coupled to a source S of the-NMOS transistor MN4, and a base B coupled to a second terminal of the substrate resistor Rsub1. The current source Igen is coupled between the drain D of the NMOS transistor MN4 and the base B of the bipolar transistor Q4. Electron-hole pairs (EHPs) are generated by a high voltage due to an ESD event that is applied to the drain D in a depletion layer formed at a junction of the drain area of the gate-coupled NMOS transistor and the backside SUB of the semiconductor substrate. A current based on the electron-hole pairs (EHPs) is denoted by Igen. The bipolar transistor Q4, which is connected in parallel with the NMOS transistor MN4, is operated using the current generated based on the electron-hole pairs (EHPs) as a base current. The substrate resistor Rsub1 represents a resistor between the base of the bipolar transistor Q4 and the backside of the semiconductor substrate SUB.
When simulating an integrated circuit included in a semiconductor device, it is required that the simulation be performed considering an ESD characteristic of not only the gate-coupled MOS transistor, but also all of the MOS transistors included in the integrated circuit.
Polarities of the drain and source can be changed according to voltages applied thereto. For example, a high voltage can be applied to a drain and a low voltage can be applied to a source. In contrast, a low voltage can be applied to a drain and a high voltage can be applied to a source.